Semiconductor memory device having potential amplitude of global bit line pair restricted to partial swing

ABSTRACT

A local sense amplifier drives a global bit line pair by potentials of data storage nodes when a global word line attains an H level. A global sense amplifier amplifies the potential difference of data storage nodes when a global sense enable signal attains an H level. The global sense enable signal is inverted by an inverter to be provided to a global word driver. When the global word line attains an L level by the global word driver, the local sense amplifier suppresses the drive of the global bit line pair.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor memory device,particularly to the technique of lowering power consumption in a staticrandom access memory (SRAM).

[0003] 2. Description of the Background Art

[0004] In accordance with the reduction in power consumption ofelectrical equipment in these years, there have been intensive effortsto reduce power consumption of semiconductor memory devices employed insuch electronic equipment.

[0005] As one method of partially achieving low power consumption ofsemiconductor memory devices, Japanese Patent Laying-Open No. 7-161192discloses the provision of a first transfer gate between a bit line pairand a sense amplifier to prevent full swing of the potential of the bitline pair isolated from the first transfer gate.

[0006] In an SRAM having the memory cell array divided into a pluralityof blocks, the global bit line connecting respective blocks of memorycells still attains a full swing even though the potential amplitude ofthe bit line is restricted to a partial swing as described above. Powerconsumption is particularly noticeable when there are many outputterminals.

SUMMARY OF THE INVENTION

[0007] An object of the present invention is to provide a semiconductormemory device having the potential amplitude of a global bit line pairrestricted to a partial swing.

[0008] According to an aspect of the present invention, a semiconductormemory device includes a sense amplifier group configured in hierarchyto read out data from a memory cell, a complementary signal line groupconnecting a sense amplifier of a lower hierarchy level and a senseamplifier of a higher hierarchy level, and a control circuit suppressingthe drive of complementary signal lines by the sense amplifier of thelower hierarchy level connected to the complementary signal lines, andrendering active the sense amplifier of the upper hierarchy levelconnected to the complementary signal lines, before the potentialdifference between the complementary signal lines arrives at the levelof the power supply voltage.

[0009] According to the semiconductor memory device of the presentinvention, the potential amplitude can be restricted to a partial swingin a global bit line pair, in addition to a local bit line pair and alocal data line pair.

[0010] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 shows a structure of a main part of an SRAM according to afirst embodiment of the present invention.

[0012]FIG. 2 shows a structure of a local sense amplifier SA1 of thefirst embodiment.

[0013]FIG. 3 shows a structure of a global sense amplifier HSA of thefirst embodiment.

[0014]FIG. 4 is a timing chart to describe a data readout operation ofthe SRAM of the first embodiment.

[0015]FIG. 5 shows a structure of a SRAM according to a background art.

[0016]FIG. 6 shows a structure of a local sense amplifier SA0 accordingto a background art.

[0017]FIG. 7 shows a structure of a main part of an SRAM according to asecond embodiment of the present invention.

[0018]FIG. 8 shows a structure of a global write driver HDR1 of thesecond embodiment.

[0019]FIG. 9 shows a structure of a local write driver DR0 of the secondembodiment.

[0020]FIG. 10 shows a structure of a main part of an SRAM according to athird embodiment of the present invention.

[0021]FIG. 11 shows a structure of a global write driver HDR2 of thethird embodiment.

[0022]FIG. 12 shows a structure of a local write driver DR2 of the thirdembodiment.

[0023]FIG. 13 shows a structure of a main part of an SRAM according to afourth embodiment of the present invention.

[0024]FIG. 14 shows a structure of a local sense amplifier SA2 equippedwith a write function of the fourth embodiment.

[0025]FIG. 15 shows a structure of a main part of an SRAM according to afifth embodiment of the present invention.

[0026]FIG. 16 shows a structure of a local sense amplifier SA3 equippedwith a write function of the fifth embodiment.

[0027]FIG. 17 shows a structure of a main part of an SRAM according to asixth embodiment of the present invention.

[0028]FIG. 18 shows a structure of a global write driver HDR3 of thesixth embodiment.

[0029]FIG. 19 shows a structure of a local sense amplifier SA4 equippedwith a write function of the sixth embodiment.

[0030]FIG. 20 shows a structure of a local write driver DR150 of thesixth embodiment.

[0031]FIG. 21 shows a structure of a main part of an SRAM according to aseventh embodiment of the present invention.

[0032]FIG. 22 shows a structure of a local sense amplifier SA5 of theseventh embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] Embodiments of the present invention will be describedhereinafter with reference to the drawings.

[0034] First Embodiment

[0035] The first embodiment of the present invention is directed to asemiconductor memory device having the potential amplitude restricted toa partial swing in a global bit line pair.

[0036] Entire Structure

[0037] Referring to FIG. 1, an SRAM according to the first embodiment ofthe present invention has a memory cell array MA divided into aplurality of blocks in the bit line direction. By dividing the memorycell array MA, the number of memory cells M connected to a selected bitline pair can be reduced to lower the parasitic capacitance of the bitline pair, leading to lower power consumption.

[0038] Each block is supplied with n row address signal, respectivelydiffering for each block. Specifically, the row address signals X<0> toX<n−1> are applied to the 0th block. Row address signals X<n> to X<2n−1>are applied to the first block. In FIG. 1, the circuit configuration ofthe 0th block is depicted. The remaining blocks have a similar circuitconfiguration.

[0039] Word line drivers G10 and G11 drive word lines WD<0> and WD<n−1>,respectively. A word line driver is provided corresponding to each wordlines. In FIG. 1, only word line drivers G10 and G11 are depictedrepresentative thereof.

[0040] Each word line has m memory cells M connected.

[0041] In each block, m local bit line pairs BT<0>, BTC<0>, . . .BT<m−1>, BTC<m−1> are provided. Each memory cell M is connected to anappropriate one of the bit line pairs.

[0042] Column addresses Y<0> to Y<m−1> are applied common to each block.One bit line pair is selected in response to any one of the columnaddresses being set at an H level (logical high). The selected bit linepair is connected to a pair of local data lines DATA and DATAC viatransmission gates T10-T13.

[0043] A dummy column DC generates a local sense enable signal SE<0>that is an activation signal of a local sense amplifier SA1<0>.

[0044] A global dummy column HDC controls the activation of global wordlines HWD<0>, HWD<1> . . . , and generates a global sense enable signalHSE controlling activation of a global sense amplifier HSA.

[0045] Structure of Local Sense Amplifier SA1

[0046]FIG. 2 shows a structure of a local sense amplifier SA1<0> of thefirst embodiment. Local sense amplifier SA1<0> is a local senseamplifier provided corresponding to the 0th block. All the local senseamplifiers SA1<0>, SA1<1> . . . are indicated generically as local senseamplifier SA1. Similarly, all the local bit line pairs and global wordlines are indicated generically as local bit line pair BT, BTC, andglobal word line HWD, respectively.

[0047] Local sense amplifier SA1<0> has its input terminal connected tolocal data line pair DATA, DATAC, and its output terminal connected toglobal bit line pair HBT, HBTC.

[0048] When local sense enable signal SE<0> is at an L level (logicallow), P channel MOS transistors P20 and P21 conduct. In response, thepotential of local data line DATA is set at a data storage node D20whereas the potential of local data line DATAC is set at a data storagenode D21.

[0049] When local sense enable signal SE<0> attains an H level, Nchannel MOS transistor N20 conducts. In response, amplification isconducted so that the potentials of data storage nodes D20 and D21 areset so that one attains the level of VDD and the other attains the levelof GND.

[0050] When global word line HWD<0> attains an H level, N channel MOStransistors N21 and N22 conduct. In response, the potential of datastorage node D20 is driven to global bit line HBT whereas the potentialof data storage node D21 is driven to global bit line HBTC. Accordingly,local sense amplifier SA1<0> operates as a sense amplifier to amplifythe potential difference of local data line pair DATA, DATAC, and alsooutputs a potential corresponding to stored data to global bit line pairHBT, HBTC, corresponding to the operation of a memory cell.

[0051] When global word line HWD<0> attains an L level, N channel MOStransistors N21 and N22 are rendered non-conductive. In response, thedrive of global bit line HBT by the potential of data storage node D20as well as the drive of global bit line HBTC by the potential of datastorage node D21 is suppressed.

[0052] Structure of Global Sense Amplifier HSA

[0053]FIG. 3 shows a structure of a global sense amplifier HSA of thefirst embodiment. Following the generation of sufficient potentialdifference between global bit lines HBT and HBTC, global sense enablesignal HSE output from global dummy column HDC attains an H level. Inresponse, N channel MOS transistor N30 is rendered conductive, whereas Pchannel MOS transistors P30 and P31 are rendered non-conductive. Thepotential of one of data storage nodes D30 and D31 attains the level ofVDD whereas the other attains the level of GND.

[0054] In response to the next rise of clock CLK, global sense enablesignal HSE attains an L level. The potentials of data storage nodes D30and D31 are retained at a latch circuit formed of two NAND gates G30 andG31.

[0055] Read Out Operation

[0056] A data read out operation will be described with reference to thetiming chart of FIG. 4.

[0057] During the period of time where clock CLK is at an L level, and aclock CLK1 that is a delayed version of clock CLK by a predeterminedtime through a delay circuit DLY is at an L level, a prechargedoperation set forth below is carried out.

[0058] All local bit line pairs BT, BTC are set at an H level when clockCLK is at an L level.

[0059] In dummy column DC, P channel MOS transistor P10 is renderedconductive when clock CLK is at an L level. In response, dummy bit lineDBT is set at an H level. This H level of dummy bit line DBT is invertedby an inverter G14. Local sense enable signal SE<0> is set at an Llevel.

[0060] In global dummy column HDC, P channel MOS transistor P13 isrendered conductive when clock CLK1 is at an L level. In response,global dummy bit line HDBT is set at an H level. This H level of globaldummy bit line HDBT is inverted by an inverter G18. Global sense enablesignal HSE is set at an L level.

[0061] When clock CLK1 is at an L level, P channel MOS transistors P11and P12 conduct. Accordingly, global bit line pair HBT, HBTC is set atan H level.

[0062] In local sense amplifier SA1<0>, P channel MOS transistors P20and P21 are rendered conductive whereas N channel MOS transistor N20 isrendered non-conductive when local sense enable signal SE<0> is at an Llevel. In response, the potential on local data line DATA is applied todata storage node D20 of a latch & amplify circuit LAT20, whereas thepotential of local data line DATAC is supplied to data storage node D21of latch & amplify circuit LAT20.

[0063] In global sense amplifier HSA, P channel MOS transistors P30 andP31 are rendered conductive whereas N channel MOS transistor N30 isrendered non-conductive when global sense enable signal HSE is at an Llevel. In response to the conduction of P channel MOS transistors P30and P31, the potentials of global bit line pair HBT, HBTC aretransferred to data storage nodes D30 and D31, respectively.

[0064] Then, a read out operation is initiated when clock CLK is pulledup to an H level at time t0.

[0065] Specifically, in synchronization with the rise of clock CLK (FIG.4, (1)), the external address is rendered valid. At the elapse of aperiod of time required for address decoding, one memory cell M isselected through all the blocks. In the following, description is basedon the case where a memory cell M is selected, specified by a rowaddress signal X<0> and a column address signal Y<0> of the 0th block.

[0066] When row address X<0> attains an H level, word line WD<0> ispulled up to an H level at time t1 by word line driver G10 (FIG. 4,(2)). In response, data of all memory cells M connected to word lineWD<0> are output to respective-connected bit line pairs. Accordingly,the potential of one bit line of the bit line pair connected to eachmemory cell becomes lower than the level of VDD.

[0067] Then, a block select signal BS<0> and the column select signalattain an H level. Therefore, the potentials of local bit line pairBT<0> and BTC<0> are transferred to local data line pair DATA and DATAC.

[0068] In dummy column DC, N channel MOS transistor N10 is renderedconductive in response to word line WD<0> pulled up to an H level,whereby dummy bit line DBT is set at an L level. The driving capabilityof N channel MOS transistor N10 is larger than the driving capability ofthe N channel MOS transistor in the memory cell. Therefore, the rate ofthe potential drop of dummy bit line DBT is faster than the rate of thepotential drop of local bit line BT or BTC.

[0069] Inverter G14 inverts the L potential level of dummy bit line DBT.At time T2, local sense enable signal SE<0> is set at an H level (FIG. 4(3)).

[0070] N channel MOS transistor N10 (and N11) is sized so that localsense enable signal SE<0> is rendered active to an H level when thepotential difference ΔV between local data lines DATA and DATAC, i.e.,the input signal to local sense amplifier SE<0>, becomes large enough(generally, 200 mV-300 mV).

[0071] This local sense enable signal SE<0> is inverted by an inverterG15 to be provided to word drivers G10 and G11. In response, all wordlines attain a non-selected state, whereby the potential reduction ofthe bit line is ceased. In other words, no current flows from memorycell M.

[0072] In local sense amplifier SA1<0>, P channel MOS transistors P20and P21 are rendered non-conductive whereas N channel MOS transistor N20is rendered conductive when local sense enable signal SE<0> attains an Hlevel. In response, the potential difference between data storage nodesD20 and D21 is amplified. The potentials of one of data storage nodesD20 and D21 attains the level of VDD whereas the other attains the levelof GND.

[0073] At an elapse of a predetermined time defined by delay circuit DLYfrom the rise of local sense enable signal SE<0>, global word driver G16is rendered active. Global word driver G16 drives global word lineHWD<0> to an H level at time t3 (FIG. 4 (4)). Delay circuit DLY isprovided for the purpose of delaying the activation timing of globalword line HWD<0>. In other words, activation of global word line HWD<0>causes local sense amplifier SA1<0> to drive the retaining data to theglobal bit line pair. As will be described afterwards, delay circuit DLYis provided so that the data retained by local sense amplifier SA1<0> isapplied to global bit line pair HBT, HBTC after being amplifiedsufficiently.

[0074] In accordance with the delay of the activation timing of globalword line HWD<0>, the operation of global sense amplifier HSA must alsobe delayed. To this end, a clock CLK1 that is a delayed version of clockCLK by delay circuit DLY is applied to global dummy column HDC relatedto the operation of global sense amplifier HSA and to P channel MOStransistors P13, P11 and P12 directed to precharge global bit line pairHBT, HBTC.

[0075] In local sense amplifier SA1<0>, N channel MOS transistors N21and N22 are rendered conductive when global word line HWD<0> attains anH level. In response, the potential of data storage node D20 is drivento global bit line HBT whereas the potential of data storage node D21 isdriven to global bit line HBTC.

[0076] In global dummy column HDC, N channel MOS transistor NH10 isrendered conductive when global word line HWD<0> attains an H level. Inresponse, global dummy bit line HDBT is set at an L level. This L levelpotential of global dummy bit line HDBT is inverted by an inverter G18.At time t4, global sense enable signal HSE is set at an H level (FIG. 4(5)).

[0077] Since the driving capability of N channel MOS transistor NH10 isset larger than that of local sense amplifier SA1<0>, the rate of thepotential drop of global dummy bit line HDBT becomes higher than therate of the potential drop of global bit line HBT or HBTC. In thepresent specification, the driving capability of local sense amplifierSA1<0> corresponds to the amount of current flowing from N channel MOStransistor N21 to N channel MOS transistor N20 through N channel MOStransistor N25, or the amount of current flowing from N channel MOStransistor N22 to N channel MOS transistor N20 through N channel MOStransistor N26.

[0078] In global sense amplifier HSA, P channel MOS transistors P30 andP31 are rendered non-conductive whereas N channel MOS transistor N30 isrendered conductive when global sense enable signal HSE attains an Hlevel. When P channel MOS transistors P30 and P31 are renderednon-conductive, global bit line pair H is isolated from data storagenodes D30 and D31. In response to conduction of N channel MOS transistorN30 the potential difference between data storage nodes D30 and D31 isamplified. One of the potentials of data storage nodes D30 and D31attains the level of VDD whereas the other attains the level of GND. Thepotentials of data storage nodes D30 and D31 are retained at a latchformed of NAND circuits G30 and G31 to be output from a terminal DOUT.

[0079] Global sense enable signal HSE is inverted by an inverter G19 tobe provided to global word drivers G16 and G17. Accordingly, all globalword lines HWD attain a non-selected state. As a result, local senseamplifier SA1<0> suppresses the drive of global bit line pair HBT, HBTC.Therefore, reduction in the potential of global bit line pair HBT, HBTCis ceased. This ceasing timing is set to the time of one of global bitlines HBT and HBTC attaining the level of VDD−α(α=200 mV to 300 mV).This timing can be adjusted by altering the driving capability of Nchannel MOS transistors NH10 and NH11 in global dummy column HDC.

[0080] Thus, the potential amplitude of global bit line pair HBT, HBTCis restricted to a partial swing. Therefore, no current will flow fromlocal sense amplifier SA1. In other words, local sense amplifier SA1<0>suppresses the drive of global bit line pair HBT, HBTC before thepotential difference of global bit lines HBT, HBTC attains the level ofVDD, and also renders global sense amplifier HSA active.

[0081] When clock CLK attains an L level at time t5, dummy bit line DBTis set at an H level in dummy column DC. In response, local sense enablesignal SE<0> is set at an L level.

[0082] When clock CLK1 (delayed version of clock CLK) attains an Llevel, global dummy bit line HDBT is set at an H level in global dummycolumn HDC. Accordingly, global sense enable signal HSE is set at an Llevel.

[0083] Comparison With SRAM According to Background Art

[0084] The SRAM of the first embodiment will be compared with a SRAMaccording to a background art whose structure is shown in FIG. 5. TheSRAM of FIG. 1 differs from the SRAM according to a background art ofFIG. 5 in that a global bit line pair HBT, HBTC is provided instead ofglobal data line HDATA of the SRAM according to a background art, alocal sense amplifier SA1 is provided instead of local sense amplifierSA0, and a global sense amplifier HSA and a global dummy column HDC areprovided, absent in the SRAM according to a background art.

[0085]FIG. 6 shows a structure of a local sense amplifier SA0<0>according to a background art. When local sense enable signal SE<0>attains an H level in local sense amplifier SA0<0>, P channel MOStransistors P20 and P21 are rendered non-conductive whereas N channelMOS transistor N20 is rendered conductive. In response, the potentialdifference between data storage nodes D20 and D21 is amplified, wherebyone of the potentials of data storage nodes D20 and D21 attain a VDDlevel whereas the other attains a GND level.

[0086] When block select signal BS<0> attains an H level in an outputbuffer DR200, a P channel MOS transistor P203 and an N channel MOStransistor N201 are rendered conductive. Therefore, when the potentialof data storage node D20 is at an L level, N channel MOS transistor N202is rendered conductive. The potential of global data line HDATA attainsan L level. When the potential of data storage node D20 attains an Llevel, P channel MOS transistor P202 is rendered conductive. Thepotential of global data line HDATA attains an L level.

[0087] Thus, the global data line HDATA according to a background artattains a full swing whereas the potential amplitude of global bit linepair HBT, HBTC is restricted to a partial swing in the SRAM of thepresent embodiment. Therefore, power consumption can be reduced.

[0088] In the SRAM of the present embodiment, data can be read out froma memory cell in hierarchy by a local memory circuit formed of localdata line pair DATA, DATAC, word line WD, dummy column DC, and localsense amplifier SA1 operating in a manner similar to that of a globalmemory circuit formed of global bit line pair HBT, HBTC, global wordline HWD, global dummy column HDC and global sense amplifier HSA.Although the present embodiment is based on a hierarchy structure of twolevels, the present invention can be extended to a hierarchy structureof more than two levels. For example, in a hierarchy of three levels,the memory cell array is divided into 2 stages. Specifically, the memorycell array is first divided into large blocks, and then furthersubdivided into smaller blocks. A plurality of global memory circuitscan be provided corresponding to the subblocks, and one global memorycircuit can be provided corresponding to the large blocks.

[0089] Second Embodiment

[0090] The second embodiment is directed to an SRAM having a writefunction added to the SRAM of the first embodiment.

[0091] Entire Structure

[0092]FIG. 7 shows a structure of a main part of an SRAM of the secondembodiment. FIG. 7 depicts only the structure of circuitry required forwriting to the 0th block. The SRAM of the second embodiment correspondsto the SRAM of FIG. 1, provided that a global write driver HDR1 andlocal write drivers DR0 and DR1 are added. These additional elementswill be described hereinafter.

[0093] Global Write Driver HDR1

[0094]FIG. 8 shows a structure of global write driver HDR1 of the secondembodiment. A write designation signal WE, a delay clock CLK1, and writedata Din are input to global write driver HDR1. Externally applied writedesignation signal WE attains an H level when writing is designated.

[0095] Global write signal WE1 attains an H level only when writedesignation signal WE is at an H level and delay clock CLK1 is at an Hlevel. When global write signal WE1 is at an H level, P channel MOStransistors P61 and P63 conduct. Also, N channel MOS transistors N61 andN63 conduct.

[0096] When write data Din is at an H level in such a case, N channelMOS transistor N61 and P channel MOS transistor P64 are renderedconductive. The data of global bit line HBT attains an L level, whereasthe data of global bit line HBTC attains an H level. In the case wherewrite data Din is at an L level, P channel MOS transistor P62 and Nchannel MOS transistor N64 are rendered conductive. The data of globalbit line HBT attains an H level whereas the data of global bit line HBTCattains an L level.

[0097] When write designation signal WE is at an L level or delay clockCLK1 is at an L level, global write driver HDR1 provides a highimpedance output to global bit line pair HBT, HBTC.

[0098] Local Write Drivers DR0, DR1

[0099]FIG. 9 shows a structure of a local write driver DR0 of thepresent embodiment. A global write signal WE1, a block select signalBS<0>, and the data of global bit line HBT are applied to local writedriver DR0. Local write driver DR0 provides a data output to local dataline DATA. Externally applied block select signal BS<0> attains an Hlevel when the 0th block is selected.

[0100] When global write signal WE1 is at an H level and block selectsignal BS<0> is at an H level, NAND gate 71 provides an output of an Llevel. P channel MOS transistor P71 and N channel MOS transistor N71conduct.

[0101] When the data of global bit line HBT is at an H level in such acase, N channel MOS transistor N72 is rendered conductive. The data oflocal data line DATA attains an L level. When the data of global bitline HBT attains an L level, N channel MOS transistor P72 is renderedconductive. The data of local data line DATA attains an H level.

[0102] When global write signal WE1 is at an L level or when blockselect signal BS<0> is at an L level, local write driver DR0 provides ahigh impedance output to local data line pair DATA, DATAC.

[0103] The structure of local write driver DR1 is similar to that oflocal write driver DR0 described previously. Therefore, the descriptionof the structure of local write driver DR1 will not be repeated. In thecase where global write signal WE1 is at an H level and block selectsignal BS<0> is at an H level, local write driver DR1 drives the data oflocal data line DATAC to an L level and an H level when the data onglobal bit line HBTC is at an H level and an L level, respectively.

[0104] Thus, the data driven to local data line pair DATA, DATAC iswritten into the target memory cell by the selection of local word lineWD and local bit line pair BT, BTC.

[0105] According to the SRAM of the second embodiment, not only a readout operation, but also a write operation, can be carried out inhierarchy.

[0106] The present embodiment is based on a structure in which two localwrite drivers DR0 and DR1 are provided corresponding to one block. Thetwo local write drivers DR0 and DR1 can be taken as one local writedriver.

[0107] Third Embodiment

[0108] The third embodiment is directed to an SRAM dispensable of awrite signal WE1 used to control a writing operation in the previoussecond embodiment.

[0109] Entire Structure

[0110]FIG. 10 shows a structure of a main part of an SRAM of the thirdembodiment. FIG. 10 depicts only the structure of circuitry required forwriting to the 0th block. The SRAM of the third embodiment shown in FIG.10 differs from the SRAM of the second embodiment shown in FIG. 7 in theinclusion of a global write driver HDR2 instead of global write driverHDR1, and one local write driver DR2 instead of two local write driversDR0 and DR1. These elements will be described hereinafter.

[0111] Structure of Global Write Driver HDR2

[0112]FIG. 11 shows a structure of global write driver HDR2 of the thirdembodiment. A write designation signal WE, a delay clock CLK1, and writedata Din are input to global write driver HDR2.

[0113] Only when both write designation signal WE and delay clock CLK1attain an H level, P channel MOS transistors P61 and P63 are renderedconductive and N channel MOS transistors N61, N63 and N64 are renderedconductive. Accordingly, the data of global bit line HBTC attains an Llevel. Thus, the present embodiment is characterized in that, whenwriting is designated through write designation signal WE, global bitline HBTC is set at an L level instead of global write signal WE1 beingset at an H level.

[0114] When write data Din is at an H level in this case, N channel MOStransistor N62 is rendered conductive. The data of global bit line HBTattains an L level. In contrast, when write data Din is at an L level, Pchannel MOS transistor MOS transistor P62 is rendered conductive. Dataof global bit line HBT attains an H level. Accordingly, write data Dinis driven to global bit line HBT.

[0115] In the case where write designation signal WE is at an L level ordelay clock CLK1 is at an L level, global write driver HDR2 provides ahigh impedance output to global bit line pair HBT, HBTC.

[0116] Structure of Local Write Driver DR2

[0117]FIG. 12 shows a structure of local write driver DR2 of the presentembodiment. The data on local bit line HBT, block select signal BS<0>,and the data on global bit line HBTC are applied to local write driverDR2.

[0118] P channel MOS transistors P102 and P104, and N channel MOStransistors N102 and N104 are rendered conductive only when block selectsignal BS<0> is at an H level and global bit line HBTC is at an L level.

[0119] When global bit line HBT is at an H level in such a case, Nchannel MOS transistor N103 and P channel MOS transistor P101 arerendered conductive. Accordingly, the data of local data line DATAattains an L level whereas the data of local data line DATAC attains anH level.

[0120] When global bit line HBT attains an L level, P channel MOStransistor P103 and N channel MOS transistor N101 are renderedconductive. Accordingly, the data of local data line DATA attains an Hlevel whereas the data of local data line DATAC attains an L level.

[0121] When block select signal BS<0> is at an L level, or when globalbit line HBTC is at an H level, local write driver DR2 provides anoutput of high impedance to local data line pair DATA, DATAC.

[0122] Relationship with Read Out Operation

[0123] It is appreciated from the above description that local writedriver DR2 uses global bit line HBTC for write control. In a read outmode, this local bit line HBTC may be set to an L level. Erroneousdesignation of writing must be obviated for local write driver DR2 whenglobal data line HBTC attains an L level in a data read mode. This isrealized as set forth below.

[0124] As described in the first embodiment, global bit line pair HBT,HBTC does not attain a full swing in a read mode. In other words, thepotential drop of global bit line HBTC is restricted to 200 mV to 300mV. Therefore, the threshold value of input inverter 104 of local writedriver DR2 is set lower than 200 mV. Accordingly, input inverter 104provides an output of an L level even if global bit line HBTC is set atan L level in a read mode since the potential is in the range of 200 mVto 300 mV. When global bit line HBTC is set at an L level indicatingwrite designation in a write mode, input inverter 104 provides an Hlevel output. Therefore, even if global data line HBTC attains an Llevel by a data read out operation, local write driver DR2 will notaccept the pull down of global data line HBTC to an L level as writingdesignation.

[0125] When global bit line HBTC is at an L level, global bit line HBTattains an H level in a read mode. Global bit lines HBT, HBTC attainsuch potential level since local data lines DATA and DATAC attain an Hlevel and an L level, respectively, by the data read out from memorycell M.

[0126] In this case, in response to global bit line HBTC attaining an Llevel, local write driver DR2 drives local data lines DATA and DATAC toan L level and an H level, respectively. Accordingly, data is writteninto memory cell M. However, the data in memory cell M will not change.

[0127] According to the SRAM of the third embodiment, the signal line ofwrite signal WE1 is dispensable by sending write designation through aglobal bit line. The circuitry area can be reduced. Also, powerconsumption can be reduced.

[0128] Fourth Embodiment

[0129] The fourth embodiment of the present invention is directed to anSRAM having a sense amplifier and write driver combined.

[0130] Entire Structure

[0131]FIG. 13 shows a structure of a main part of an SRAM of the fourthembodiment. FIG. 13 shows only a structure of circuitry required forwriting to the 0th block. The SRAM of the fourth embodiment differs fromthe SRAM of the second embodiment shown in FIG. 7 in that one localsense amplifier SA2 equipped with a write function is provided insteadof a local sense amplifier SA1 and two local write drivers DR0 and DR1.These elements will be described hereinafter.

[0132] Structure of Local Sense Amplifier SA2 Equipped with a WriteFunction

[0133]FIG. 14 shows a structure of a local sense amplifier SA2<0>equipped with a write function of the fourth embodiment. This localsense amplifier SA2<0> has transmission gates TG120 and TG121 added tolocal sense amplifier SA1<0> of FIG. 2. Transmission gates TG120 andTG121 are under control of control signals QN and QP. Control signals QNand QP are generated by a NAND gate G122 and an inverter 123 based onglobal write signal WE1 and block select signal BS<0>.

[0134] Control signals QN and QP attain an H level and an L level,respectively, only when both global write signal WE1 and block selectsignal BS<0> are at an H level. In this case, transmission gates TG120and TG121 are rendered conductive. As a result, global bit line pairHBT, HBTC is connected with global data line pair DATA, DATAC.

[0135] When global write signal WE1 is at an L level or block selectsignal BS<0> is at an L level, control signals QN and QP attain an Llevel and an H level, respectively. Transmission gates TG120 and TG121are rendered non-conductive. As a result, global bit line pair HBT, HBTCis not connected with local data line pair DATA, DATAC.

[0136] The operation of local sense amplifier SA2<0> equipped with awrite function will be described hereinafter, corresponding to a readoperation and a write operation.

[0137] Read Operation

[0138] In a read mode, transmission gates T120 and TG121 are renderednon-conductive since global write signal WE1 is at an L level.Therefore, global bit line pair HBT, HBTC is not connected with localdata line pair DATA, DATAC. In this case, local sense amplifier SA2<0>operates in a manner similar to that of local sense amplifier SA1<0> ofFIG. 2.

[0139] Write Operation

[0140] In a write mode, global write signal WE1 is at an H level.Therefore, transmission gates TG120 and TG121 are rendered conductivewhen block select signal BS<0> is at an H level. Accordingly, global bitline pair HBT, HBTC is connected with local data line pair DATA, DATAC.

[0141] Global bit line pair HBT, HBTC has the data to be written outputby global write driver HDR1. Therefore, the relevant data aretransferred to local data lines DATA, DATAC via transmission gates TG120and TG121 attaining a conductive state.

[0142] By just adding two transmission gates TG120 and TG121, a NANDgate G122 and an inverter G123 to the local sense amplifier in thepresent embodiment, the local sense amplifier can also function as alocal write driver. The number of elements can be reduced than in thesecond embodiment where a single local write driver is provided.Accordingly, the circuitry area can be reduced. Also, power consumptioncan be reduced.

[0143] Fifth Embodiment

[0144] The fifth embodiment is directed to an SRAM that drives localdata line pair DATA, DATAC, absent of a transmission gate. In theprevious fourth embodiment, local sense amplifier SA2 equipped with awrite function has local data line pair DATA, DATAC driven viatransmission gates. It is known that, since the transmission gate has alow driving capability, one of the potentials of local data lines DATA,DATAC cannot be set low enough when the parasitic capacitance of localdata line pair DATA, DATAC is large. This means that data cannot bewritten into a memory cell. The present embodiment is directed toovercome such a problem.

[0145] Entire Structure

[0146]FIG. 15 shows a structure of a main part of an SRAM according tothe fifth embodiment. FIG. 15 shows only the structure of circuitryrequired for writing to the 0th block. The SRAM of the fifth embodimentdiffers from the SRAM of the fourth embodiment shown in FIG. 13 in thata local sense amplifier SA3 equipped with a write function is providedinstead of local sense amplifier SA2 equipped with the write function.

[0147] Structure of Local Sense Amplifier SA3

[0148]FIG. 16 shows a structure of a local sense amplifier SA3<0>equipped with a write function of the fifth embodiment. Local senseamplifier SA3<0> of the fifth embodiment differs from local senseamplifier SA2<0> of FIG. 14 in that global bit line pair HBT, HBTC willnot be directly connected with local data line pair DATA, DATAC. Also, Nchannel MOS transistors N131 and N132 are added between local data linepair DATA, DATAC and data storage nodes D20 and D21 in latch & amplifycircuit LAT20. Furthermore, an OR gate G130, an AND gate G131 and an ORgate G132 are also added.

[0149] The operation of local sense amplifier SA3<0> equipped with awrite function will be described, corresponding to a read mode and awrite mode.

[0150] Read Operation

[0151] In a read out mode, local sense amplifier SA3<0> operates in amanner similar to that of local sense amplifier SA1<0> shown in FIG. 2,as set forth below.

[0152] Since global write signal WE1 is at an L level in a read mode,AND gate G131 provides an L level output. In response, N channel MOStransistors N131 and N132 are rendered non-conductive.

[0153] P channel MOS transistors P20 and P21 conduct during an L levelperiod of local sense enable signal SE<0>. Accordingly, the potentialsof local data lines DATA, DATAC are set at data storage nodes D20 andD21.

[0154] Then, P channel MOS transistors P20 and P21 are renderednon-conductive during an H level period of local sense enable signalSE<0>. Also, since OR gate G132 provides an H level output, N channelMOS transistor N20 is rendered conductive. Accordingly, the potentialdifference between data storage nodes D20 and D21 is amplified. One ofthe potentials of data storage nodes D20 and D21 attains a VDD levelwhereas the other attains the GND level.

[0155] When global word line HWD<0> attains an H level, N channel MOStransistors N21 and N22 conduct since OR gate G130 provides an H leveloutput. Accordingly, the potentials of data storage nodes D20 and D21are transferred to global bit line pair HBT, HBTC.

[0156] Write Operation

[0157] In a write operation, global write signal WE1 is at an H level.Therefore, OR gate G130 provides an H level output when block selectsignal BS<0> is at an H level. Accordingly, N channel MOS transistorsN21 and N22 are rendered conductive. Therefore, the potentials of globalbit line pair HBT, HBTC corresponding to the write data are set at datastorage nodes D20 and D21. At this stage, N channel MOS transistor N20is also rendered conductive since OR gate G132 provides an H leveloutput. Thus, write data is fetched into latch & amplify circuit LAT20.

[0158] At this stage, N channel MOS transistors N131 and N132 arerendered conductive since AND gate G131 provides an H level output.Accordingly, one of local data lines DATA and DATAC is discharged basedon the write data in latch & amplify circuit LAT20, whereby thepotential falls to the level of GND.

[0159] Since local data line pair DATA, DATAC and latch & amplifycircuit LAT20 are connected via N channel MOS transistors (N131, N132),the potential of one of the local data lines can be lowered to the levelof GND. In the case where a P channel MOS transistor is employed insteadof an N channel MOS transistor, the potential of the local data line canbe reduced only down to the level of threshold voltage Vthp of the Pchannel MOS transistor.

[0160] Thus, the potential of one of local data lines DATA, DATACcharged to the level of VDD can be reduced down to the GND level duringa precharge period.

[0161] According to the SRAM of the present embodiment, local data linepair DATA, DATAC is driven via N channel MOS transistors N31 and N132establishing connection between latch & amplify circuit LAT20 and localdata line pair DATA, DATAC based on the write data set at global bitline pair and applied to latch & amplify circuit LAT20. Therefore, datacan be written into a memory cell even in the case where local bit linepair BT, BTC has a large parasitic capacitance.

[0162] Sixth Embodiment

[0163] The sixth embodiment of the present invention is directed to anSRAM having the potential amplitude of a global bit line pair restrictedto a partial swing in a write mode. In the previous second to fifthembodiments, the potential of one of global bit lines HBT and HBTC isset at the level of VDD whereas the other is set at the level of GND ina write mode. When the potentials of global bit lines HBT and HBTCattain a full swing in a write mode, power consumption will beincreased. There is also a possibility of erroneous writing carried outas set forth below.

[0164] In a write mode, the word line connected to a target memory cellof writing is rendered active, and write data is set at the bit linepair connected to the memory cell of interest. The word line renderedactive has a plurality of memory cells connected other than those of thesubject of writing. These memory cells will also attain a writableselected state, likewise the memory cell subject to writing. This iscalled a pseudo selected state.

[0165] Global bit lines HBT, HBTC and local bit lines BT, BTC areinterconnected with separate interconnection layers. Theseinterconnections are arranged so as to be in parallel. As a result,parasitic capacitance is established between the interconnections. Inthe case where the potential of the global bit line changes greatlythrough the parasitic capacitance, this potential change is propagatedto the local bit line. This is referred to as “capacitive coupling”.

[0166] If the potential of the global bit line attains a full swing bysuch capacitive coupling, this potential change will be propagated tothe bit line pair connected to the memory cell attaining a pseudoselected state. As a result, erroneous writing to the pseudo selectedcell will be conducted. The present embodiment is directed to preventsuch erroneous writing as well as to reduce power consumption byrestricting the potential amplitude of a global bit line pair to apartial swing.

[0167] Entire Structure

[0168]FIG. 17 shows a structure of a main part of an SRAM of the sixthembodiment. FIG. 17 shows only a structure of circuitry required forwriting to the 0th block. The SRAM of the sixth embodiment differs fromthe SRAM of the fifth embodiment shown in FIG. 15 in that a global writedriver HDR3 is provided instead of global write driver HDR1, and a localsense amplifier SA4 equipped with a write function is provided insteadof local sense amplifier SA3 equipped with a write function. Thestructural elements will be described hereinafter.

[0169] Global Write Driver HDR3

[0170]FIG. 18 shows a structure of global write driver HDR3 of the sixthembodiment. This global write driver HDR3 has a circuit structuresimilar to that of global write driver HDR1 of the second embodimentshown in FIG. 8, provided that one of the potentials supplied to globalwrite driver HDR3 is at the level of VP instead of GND.

[0171] Potential VP is higher in level than potential GND. If thepotential drop of the global bit line in a write mode is to be set equalto that of a read mode, potential VP is to be set at a level lower thanVDD by approximately 200-300 mV. This potential VP may be applied froman external source, or generated within the SRAM.

[0172] Local Sense Amplifier SA4 Equipped with Write Function FIG. 19shows a structure of a local sense amplifier SA4<0> equipped with awrite function according to the sixth embodiment. Local sense amplifierSA4<0> differs from local sense amplifier SA3<0> of the fifth embodimentshown in FIG. 16 in that P channel MOS transistors P150 and P151 as wellas local write drivers DR150 and DR151 are added. Also, N channel MOStransistors N131 and N132 are removed, and a NAND gate G152, invertersG151 and G155, a delay circuit DLY2, and an AND gate G150 areadditionally provided.

[0173] Local Write Drivers DR150, DR151

[0174]FIG. 20 shows a structure of a local drive driver DR150 of thesixth embodiment. Local write driver DR150 receives the potential ofdata storage node D20 through a terminal IN and receives the potentialoutput from AND gate G131 through a terminal C.

[0175] AND gate G131 provides an H level output, whereby P channel MOStransistor P 161 and N channel MOS transistor N 161 are renderedconductive only when both a global write signal WE 1 and block selectsignal BS<0> attain an H level. If the potential of data storage nodeD20 is at an H level in this stage, an L level output is provided tolocal data line DATA. When the potential of data storage node D20attains an L level, an H level output is provided to local data lineDATA.

[0176] The structure of local write driver DR151 is similar to that oflocal write driver DR150 described above. Therefore, illustrationthereof will not be repeated. When global write signal WE1 and blockselect signal BS<0> are at an H level, local write driver DR151 providesan L level output and an H level output to local data line DATAC whenthe potential of data storage node D21 is at an H level and an L level,respectively.

[0177] A read operation and write operation of the SRAM of the sixthembodiment will be described hereinafter.

[0178] Read Operation

[0179] In a read mode, AND gate G131 provides an L level output sinceglobal write signal WE 1 is at an L level in local sense amplifierSA4<0> equipped with a write function. Accordingly, local write driversDR150 and DR151 provide a high impedance output. Since NAND gate G152provides an H level output, P channel MOS transistors P150 and P151 arerendered non-conductive. AND gate G150 provides an output of a logiclevel identical to that of global word line HWD<0>.

[0180] Thus, the read operation of the present embodiment is similar tothe read operation of the previous fifth embodiment.

[0181] Write Operation

[0182] In a write operation mode, global write driver HDR3 drives one ofthe potentials of global bit lines HBT and HBTC to the level of VDD andthe other potential to the level of VP according to write data Din.

[0183] Since global write signal WE1 is at an H level in local senseamplifier SA4<0> equipped with a write function, AND gate G131 providesan H level output and NAND gate G152 provides an L level output whenblock select signal BS<0> is at an H level, whereby P channel MOStransistors P150 and P151 are rendered conductive. Accordingly, thepotential of global bit line HBT is transferred to data storage node D20the potential of global bit line HBTC is transferred to data storagenode D21.

[0184] Since data storage nodes D20 and D21 are connected to the globalbit line pair via P channel MOS transistors (P1150, P151), thepotentials of VDD and VP can be transferred without any loss to datastorage nodes D20 and D21.

[0185] In the case where an N channel MOS transistor is employed insteadof a P channel MOS transistor, the potential of only VDD−Vthn at mostcan be transferred to data storage nodes D20 and D21 when the N channelMOS transistor has a threshold voltage of Vthn. Therefore, the potentialof one of data storage nodes D20 and D21 attains the level of VDD−Vthn,whereas the potential of the other node attains the level of VP. If VP>VDD−Vthn is set in such a case, the write data cannot be properly set atdata storage nodes D20 and D21. This problem can be obviated by theusage of P channel MOS transistors.

[0186] At an elapse of a predetermined period of time defined by delaycircuit DLY2 from the conduction of P channel MOS transistors P150 andP151, OR gate G132 provides an H level output. In response, N channelMOS transistor N20 is rendered conductive. Inverter G155 provides an Llevel output. NAND gate G152 provides an H level output. In response toNAND gate G152 providing an H level output, P channel MOS transistorsP150 and P151 are rendered non-conductive.

[0187] In response to conduction of N channel MOS transistor N20, one ofthe potentials of data storage nodes D20 and D21 of latch & amplifycircuit LAT20 attains the level of VDD whereas the other attains thelevel of GND. However, the potentials of data storage nodes D20 and D21are not provided to global bit line pair HBT, HBTC since P channel MOStransistors P150 and P151 are non-conductive.

[0188] At this stage, terminal C of local write drivers DR150 and DR151receives an H level input. Accordingly, the data of data storage nodeD20 is driven to local data line DATA, whereas the data of data storagenode D21 is driven to local data line DATAC.

[0189] Thus, in a read mode, local sense amplifier SA4 equipped with awrite function receives the potentials of the local data line pairattaining a partial swing, which are amplified to a full swing by latch& amplify circuit LAT20. The amplified potential is provided to theglobal bit line pair.

[0190] In a write mode, the potentials of the global bit line pairattaining a partial swing are received to be amplified by latch &amplify circuit LAT20 up to the level of a full swing.

[0191] According to the SRAM of the sixth embodiment, the potentials ofglobal bit line pair attain a partial swing, not only in a read mode,but also in a write mode. Therefore, power consumption can be reduced.Also, erroneous writing can be prevented.

[0192] Seventh Embodiment

[0193] The seventh embodiment of the present invention is directed to anSRAM having the processing timing of a local memory circuit setseparately from that of the global memory circuit.

[0194] In the previous first embodiment, data transfer to a global bitline pair must be completed within an H level period of clock CLK inlocal sense amplifier SA1<0>. This is because local sense enable signalSE<0> will attain an L level when clock CLK is pulled down to an Llevel, whereby data storage nodes D20 and D21 of local sense amplifierSA1<0> are precharged.

[0195] To have local sense amplifier SA1<0> transfer the data to globalbit line pair HBT, HBTC before the precharge operation, the timing ofrendering global word line HWD<0> to an active H level must be setduring the period where clock CLK attains an H level.

[0196] If the clock frequency is increased, the timing of renderingactive this global word line HWD<0> must be set earlier. To this end,the delay time of delay circuit DLY that determines the activationtiming of global word line HWD<0> must be set shorter. However, ashorter delay time of delay circuit DLY is disadvantageous in that theprocesses of global sense amplifier HSA and global dummy column HDCcannot be completed. Therefore, the clock frequency could not beincreased.

[0197] The previous first embodiment was described based on a structureof the two hierarchy levels, including a local memory circuit of thelower level (local sense amplifier, local data line pair, dummy columnDC and word line) to read out data from a memory cell, and a globalmemory circuit of the higher level (global sense amplifier, global bitline pair, global dummy column, and global word line). A structure ofthree or four hierarchy levels can be implemented. In the case where thenumber of hierarchy levels is increased, the memory circuit of thehigher level will rate-determine the clock frequency. In other words,the clock frequency is determined so as to allow the processing at thememory circuit of the upper level. The seventh embodiment is directed toovercome this problem.

[0198] Entire Structure

[0199]FIG. 21 shows a structure of a main part of an SRAM according tothe seventh embodiment. The SRAM of the seventh embodiment differs fromthe SRAM of the first embodiment shown in FIG. 1 in that an externallyapplied independent clock CLK2 is applied instead of clock CLK1 that isa delayed version of signal CLK by delay circuit DLY. Clock CLK2 has afrequency identical to that of clock CLK1.

[0200] Clock CLK2 is provided to global dummy column HDC, global worddrivers G16, G17, and to P channel MOS transistors P11 and P12 forcharging global bit line pair HBT, HBTC. The structural elementsreceiving clock CLK2 effect an operation at the timing of clock CLK2.

[0201] The DRAM of the seventh embodiment includes a local senseamplifier SA5 instead of local sense amplifier SA1. The structuralelement will be described hereinafter.

[0202] Local Sense Amplifier SA5

[0203]FIG. 22 shows a structure of a local sense amplifier SA5<0> of thepresent embodiment. Local sense amplifier SA5<0> has a latch circuitLAT180 and N channel MOS transistor N180 and N channel MOS transistorsN180-N183 added to local sense amplifier SA1<0> of the first embodimentshown in FIG. 2.

[0204] The operation of local sense amplifier SA5<0> in a read mode willbe described hereinafter.

[0205] Read Operation

[0206] The read operation is similar to that of the first embodimentwith the exception of the operations of global dummy column HDC and Pchannel MOS transistors P11 and P12 until the rise of local sense enablesignal SE<0>.

[0207] In global dummy column HDC, P channel MOS transistor P13 conductswhen clock CLK2 is at an L level. Accordingly, global dummy bit lineHDBT is set at an H level. This H level potential of global dummy bitline HDBT is inverted by inverter G18. Global sense enable signal HSE isset at an L level.

[0208] When clock CLK2 is at an L level, P channel MOS transistors P11and P12 are rendered conductive. In response, global bit line pair HBT,HBTC is set at an H level.

[0209] In local sense amplifier SA5<0>, P channel MOS transistors P20and P21 are rendered conductive in response to clock CLK. The potentialof local data line DATA is transferred to data storage node D20 whereasthe potential of local data line DATAC is transferred to data storagenode D21.

[0210] In response to the rise of local sense enable signal SE<0>, Pchannel MOS transistors P20 and P21 are rendered non-conductive, whereasN channel MOS transistors N20, N182 and N183 are rendered conductive. Inresponse to non-conduction of P channel MOS transistors P20 and P21,data storage nodes D20 and D21 are isolated from local data lines DATA,DATAC. In response to conduction of N channel MOS transistor N20 thepotential of one of data storage nodes D20 and D21 attains the level ofVDD whereas the other attains the level of GND.

[0211] When the potential of data storage node D20 attains the level ofVDD, i.e., an H level, at this stage, N channel MOS transistor N181 isrendered conductive. Accordingly, a data storage node D181 of latchcircuit LAT180 is set at an L level whereas a data storage node D180 isset at an H level. Accordingly, the data of local data lines DATA, DATACare held in latch circuit LAT180. When data is once stored in latchcircuit LAT180 the data will not be lost even if clock CLK is pulleddown to an L level to cause local sense enable signal SE<0> to go low.Therefore, the rising timing of global word line HWD<0> is notrestricted to the H level period of local sense enable signal SE<0>,i.e., when clock CLK attains an H level, as in the first embodiment.

[0212] Global word driver G16 responds to clock CLK2 going high to driveglobal word line HWD<0> to an H level. In response, N channel MOStransistors N21 and N22 are rendered conductive in local sense amplifierSA5<0>. One of global bit lines HBT, HBTC is discharged to the level ofGND according to the potentials of data storage nodes D180 and D181.

[0213] When global word line HWD<0> attains an H level in global dummycolumn HDC, N channel MOS transistor NH10 is rendered conductive. Globalsense enable signal HSE attains an H level by inverter G18.

[0214] The remaining operation is similar to that of the firstembodiment.

[0215] Thus, according to the SRAM of the seventh embodiment, localsense amplifier SA5 includes a latch circuit LAT180, and the operationof the local memory circuit and the global memory circuit are based ondifferent clock signals. Therefore, the problem of the process in globalmemory circuit not being completed can be eliminated. Also, it is notnecessary to reduce the rate of the clock frequency so as to completethe processing in the global memory circuit.

[0216] Clock CLK2 may be set to be opposite in phase with clock CLK. Inthis case, the local memory circuit can operate during an H level periodof clock CLK whereas the global memory circuit can operate during an Llevel period of clock CLK.

[0217] In the case where a structure of at least three hierarchy levelsis established, the phase of the clock of each hierarchy level may beset out of phase from that of the clock of the lower hierarchy level. Inthis case, the data read out from a memory cell can be subjected to apipeline process sequentially from the memory circuit of the lowerhierarchy level. Since one cycle can be allotted to the processing timeof the memory circuit of each hierarchy level, the problem of not havingthe process completed will not occur. By the operation of the memorycircuit of each hierarchy level based on a clock directed to eachhierarchy level, a structure of three or more hierarchy levels can bereadily implemented.

[0218] Although the present invention has been described and illustratedin detail, it is clearly understood that the same is by way ofillustration and example only and is not to be taken by way oflimitation, the spirit and scope of the present invention being limitedonly by the terms of the appended claims.

What is claimed is:
 1. A semiconductor memory device comprising: a senseamplifier group configured in hierarchy to read out data from a memorycell; a complementary signal line group connecting a sense amplifier ofa lower hierarchy level with a sense amplifier of a higher hierarchylevel; and a control circuit suppressing a drive of complementary signallines by the sense amplifier of a lower hierarchy level connected tosaid complementary signal lines, and rendering active the senseamplifier of a higher hierarchy level connected to said complementarysignal lines, before a potential difference between said complementarysignal lines reaches a level of power supply voltage.
 2. Thesemiconductor memory device according to claim 1, further comprising awrite driver group configured in hierarchy to write data into a memorycell, wherein a write driver of a lower hierarchy level and a writedriver of a higher hierarchy level are connected by said complementarysignal lines and a write designation signal line, said write driver of ahigher hierarchy level outputs write data and inverted data thereof tocomplementary signal lines of a lower hierarchy level connected to saidwrite driver of a higher hierarchy level, and drives the writedesignation signal line of a lower hierarchy level connected to saidwrite driver of a higher hierarchy level at a predetermined logic value,and said write driver of a lower hierarchy level is rendered active whenthe write designation signal line of a higher hierarchy level connectedto said write driver of a lower hierarchy level attains saidpredetermined logic value.
 3. The semiconductor memory device accordingto claim 1, further comprising a write driver group configured inhierarchy to write data into a memory cell, wherein a write driver of alower hierarchy level and a write driver of a higher hierarchy level areconnected by said complementary signal lines, said write driver of ahigher hierarchy level outputs write data to one signal line ofcomplementary signal lines of a lower hierarchy level connected to saidwrite driver of a higher hierarchy level, and drives the other signalline of said complementary signal lines of a lower hierarchy level at apredetermined potential in a range other than the range of change ofsaid other signal line in a read mode, and said write driver of a lowerhierarchy level is rendered active when said other signal line attainssaid predetermined potential.
 4. The semiconductor memory deviceaccording to claim 3, wherein said write driver of a lower hierarchylevel comprises a logical element connected to said other signal line,said logical element providing an output of a first logic value when thepotential of said other signal line is in the range of change in a readmode and provides an output of a second logic value when the potentialof said other signal line is in a range other than said range.
 5. Thesemiconductor memory device according to claim 1, wherein apredetermined sense amplifier in said sense amplifier group includes atransmission gate provided between complementary signal lines of ahigher hierarchy level and complementary signal lines of a lowerhierarchy level, said transmission gate being rendered conductive whenin a data write mode.
 6. The semiconductor memory device according toclaim 1, wherein a predetermined sense amplifier in said sense amplifiergroup includes a circuit to fetch a potential of complementary signallines of a higher hierarchy level connected to said predetermined senseamplifier, and an N channel MOS transistor provided between said circuitand complementary signal lines of a lower hierarchy level connected tosaid predetermined sense amplifier, said N channel MOS transistor beingrendered conductive when in a data write mode.
 7. The semiconductormemory device according to claim 1, wherein predetermined complementarysignal lines are driven at an amplitude smaller than the amplitude ofpower supply voltage in a data write mode, wherein a sense amplifier ofa lower hierarchy level connected to said predetermined complementarysignal lines, includes an amplify circuit amplifying potentials of saidpredetermined complementary signal lines, and a P channel MOS transistorprovided between said amplify circuit and said predeterminedcomplementary signal lines, wherein, in a data write mode, said Pchannel MOS transistor is rendered conductive to have potentials of saidpredetermined complementary signal lines applied to said amplifycircuit, and after said application, said P channel MOS transistor isrendered conductive, and said amplify circuit amplifies said appliedpotentials at a logic amplitude of power supply voltage, andcomplementary signal lines of a lower hierarchy level connected to saidsense amplifier of a lower hierarchy level connected to saidpredetermined complementary signal lines are driven based on saidamplified potentials.
 8. The semiconductor memory device according toclaim 1, wherein a predetermined sense amplifier in said sense amplifiergroup includes an amplify circuit connected to complementary signallines of a lower hierarchy level, and a latch circuit connected to saidamplify circuit and connected to complementary signal lines of a higherhierarchy level, wherein said amplify circuit fetches potentials of saidcomplementary signal lines of a lower hierarchy level at a timing basedon a first clock to amplify said fetched potentials, and provide saidamplified potentials to said latch circuit, wherein said latch circuitdrives said complementary signal lines of a higher hierarchy level atlatched said amplified potentials at a timing based on a second clockdifferent from said first clock.
 9. The semiconductor memory deviceaccording to claim 8, wherein complementary signal lines of a higherhierarchy level connected to said predetermined sense amplifier areprecharged at a timing based on said second clock, and a sense amplifierof a higher hierarchy level than said predetermined sense amplifier isrendered active at a timing based on said second clock.